The present invention generally relates to multi-threshold complimentary metal oxide semiconductor (MTCMOS) designs, and more specifically relates to a fast turn-on active decoupling capacitance (DCAP) cell which can be utilized in a MTCMOS design.
For MTCMOS designs, a very short turn-on time is required for each block which has been previously powered down. All DCAP cells in a MTCMOS block have to be fully charged before the block starts to function, which imposes a stringent limit on the turn-on time of a DCAP cell that could be used in MTCMOS block.
FIG. 1 illustrates one type of prior art DCAP cell. The cell 10 is passive, and provides that a passive resistor (“R1”, identified with reference numeral 12 in FIG. 1) connects the gate 13 of an NMOS transistor (“C1”, identified with reference numeral 14 in FIG. 1) to the VDD rail 16, and another passive resistor (“R2”, identified with reference numeral 18 in FIG. 1) connects the gate 19 of a PMOS transistor (“C2”, identified with reference numeral 20 in FIG. 1) to the VSS rail 22. The cell 10 shown in FIG. 1 has a short turn-on time, but in order to minimize effective capacitance loss which is experienced at high-frequency power noises, each of the two passive resistors 12, 18 have to be provided as being sufficiently large (area) enough to make their resistance sufficiently small, which consequently leads to the major drawback of a DCAP cell which employs passive resistors—low capacitance density.
FIG. 2 illustrates another type of prior art DCAP cell—an active DCAP cell. Like the passive DCAP cell 10 shown in FIG. 1, the active DCAP cell 30 shown in FIG. 2 includes an NMOS transistor 14 and a PMOS transistor 20. However, instead of using passive resistors 12, 18 like the DCAP cell 10 shown in FIG. 1, the active DCAP cell 30 shown in FIG. 2 uses two active transistors (“M1” and “M2”, identified with reference numerals 32 and 34, respectively, in FIG. 2). When the DCAP cell 30 is fully charged, both of the transistors 32, 34 are in saturation mode and have a small resistance. Due to the transistors 32, 34 having a small resistance in saturation mode, they can be provided as being relatively small. In fact, the transistors 32, 34 in the DCAP cell 30 shown in FIG. 2 can be provided as being much smaller than the passive resistors 12, 18 of the DCAP cell 10 shown in FIG. 1. As such, the DCAP cell 30 shown in FIG. 2 successfully achieves much higher capacitance density than the DCAP cell 10 shown in FIG. 1, and ultimately reduces the chip die size. However, at the beginning of a charging, when the voltage level on the VDD rail 16 suddenly rises from 0 to VDD (due to, for example, the switch header cell being activated), because voltage across a capacitor cannot change immediately, the voltage at node “AN” (identified with reference numeral 36 in FIG. 1) remains at VSS while the voltage at node “AP” (identified with reference numeral 38 in FIG. 1) reaches VDD. Thus at this stage, both of the transistors 32, 34 are turned-off, leaving the NMOS and PMOS transistors 14, 20 to charge slowly as they receive very small leakage currents. It takes a long time to progress to the point to where AN and AP reach the threshold voltages of transistors 14, 20 and turn them on. Also, the turn-on time of the active DCAP cell 30 shown in FIG. 2 is highly dependent on the process, voltage and temperature corner, which makes the ability to control the activation of the MCTMOS block problematical.